Many devices or systems are comprised of more than one processor which communicate serially with one another. For instance, a telematics device may include two processors in serial communication with another. Similarly, the processors in a computing system may communicate serially with each other. In these configurations, a first processor may perform a plurality of applications such as performing communications, controlling the GPS, controlling the audio visual system, or other resource intensive applications. A second processor may manage components of the device in supporting the first processor. For instance, the second processor may handle I/O signals from peripherals devices or control peripheral devices on behalf of the first processor.
Typically, the second processor is a low-power processor and receives instructions in the form of messages from the first processor. One issue that arises is that the first processor may communicate multiple messages to the second processor with only milliseconds interposed between the messages. These messages will include durations indicating an amount of time that the second processor should perform the requested function, e.g., turn mute on for 10 seconds. These durations will often exceed the amount of time between two or more consecutive messages. Because the second processors are typically low-power and not as computationally capable as the first processor, an earlier message will be overridden by a later message if received before the duration of the earlier message expires. Thus, there is a need for message design that allows for more efficient and accurate communication between a high end processor and a low end processor.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.